January 27, 2017

Analog Devices AD584 - precision voltage reference : weekend die-shot

Analog Devices AD584 is a voltage reference with 4 outputs : 2.5, 5, 7.5 and 10V. Tempco is laser trimmed to <15ppm/°C and voltage error to ~0.1%.


Die size 2236x1570 µm.

One can refer to a die photo from AD datasheet showing a bit older design of the same chip:

January 16, 2017

Vishay TSOP4838 - IR receiver module : weekend die-shot

Vishay TSOP4838 - decodes IR commands sent with 38kHz modulation. This modulation (and narrow-band filter on receiver module) is required to eliminate ambient light sources which could flicker somewhere at 50-100Hz or 20-30kHz (bad CFL/LEDs). Black (IR transparent) plastic also helps with background noise.


Die size 590x594 µm.

Photodiode is on a separate die:

Die size 1471x1471 µm
December 26, 2016

ST USBLC6-2 - USB protection chip : weekend die-shot

ST USBLC6-2 has 4 diodes and 1 Zener to protect your USB gear.
Die size 1084x547 µm.


December 18, 2016

LM338K - 5A LDO in TO-3 : weekend die-shot



Die size 1834x1609 µm.

You can see why this giant package is nearly obsolete these days (it's been around since 1955) - tiny crystal on a large steel case is largely limited by steel thermal conduction. Modern packages with copper base could do better with much smaller packages.


December 18, 2016

DTA143ZK - PNP BJT with bias resistors : weekend die-shot

Comparing to Infinion BCR185W there are no even bias resistors under the pads, hence larger die size (426x424 µm).


December 15, 2016

LM1813 - early anti-skid chip : weekend die-shot

LM1813 - anti-skid chip, was the largest analog die National Semiconductor had built to date as of 1974. It was built as a custom for a brake system vendor to Ford Motor company for use in their pickup trucks.

Die size 2234x1826 µm.



Test chips on the wafer:


Thanks for the wafers goes to Bob Miller, one of designers of this chip.
December 3, 2016

CD4049 - hex CMOS inverter : weekend die-shot

On CD4049 you can see 6 independent inverters, each having 3 inverters connected in series with increasing gate width on each stage - this helps to achieve higher speed and lower input capacitance. Gate length is 6µm, so it is probably the slowest CMOS circuit one can ever see. Gates are metal (i.e. not self-aligned silicon) which are again the slower type at that time.

Die size 722x552 µm.