http://zeptobars.com/en/ Microelectronics. Die-shots. Artificial intelligence. Lasers. en-us Tue, 10 Jun 2006 04:00:00 GMT Thu, 30 Jan 25 21:01:43 +0300 webmaster@zeptobars.com 120 10 http://zeptobars.com/en/read/Analog-Devices-AD-ADE7755-Energy-Metering-IC-with-Pulse-Output

]]> Wed, 01 Jan 25 06:44:01 +0300 http://zeptobars.com/en/read/ASM3242-PCI-Express-USB3.2-20Gbps-host-controller-PCIE Die size 3719x3937um. Thanks for the ASMedia chip collection to cyrozap!


]]> Sun, 01 Dec 24 13:52:20 +0300 http://zeptobars.com/en/read/Siliconix-DG190BP-dual-SPDT-JFET-analog-switch-chiplet-Vishay
Main die size 1113x2027 µm.


]]> Sun, 17 Nov 24 06:26:37 +0300 http://zeptobars.com/en/read/Casio-F-91W-quartz-watch-homage-china Casio F-91W, but fortunately does not misuse Casio trademark. Chip is 4 times smaller in Chinese version, it looks simpler, purely digital.

PCB is optimized for cost to an extreme : everything that can be integrated is integrated. There is not even a decoupling capacitor which is probably ok for digital circuits with low slew rate.

Die size 1384x1245 µm.




]]> Wed, 30 Oct 24 17:19:39 +0300 http://zeptobars.com/en/read/Segnetics-74F651F-bus-transceiver

]]> Sun, 20 Oct 24 11:08:09 +0300 http://zeptobars.com/en/read/AD561JD-10-bit-laser-trimmed-DAC


Datasheet has top metal photo and high-level architecture:

]]> Tue, 01 Oct 24 13:26:39 +0300 http://zeptobars.com/en/read/RCA-CA3033-high-current-opamp

Schematics below:


]]> Mon, 02 Sep 24 20:04:34 +0300 http://zeptobars.com/en/read/RCA-CD40163BD-CMOS-Synchronous-Programmable-Counter

]]> Sun, 01 Sep 24 08:19:03 +0300 http://zeptobars.com/en/read/Kwazar-K140UD1B-Soviet-opamp-Ukraine-Kyiv K140UD2 which had much higher open-loop gain.

Die size 1225x1228 µm.


]]> Thu, 01 Aug 24 08:36:10 +0300 http://zeptobars.com/en/read/tt04-tinytapeout-silicon-inside-gds-sky130 TinyTapeout project (TT04) I got to design a microchip with a bunch of oscillators, had it working in my hands and inspected under microscope. Now we'll be able to verify if manufactured chip matches GDS design files and is there any secret sauce!

Feel free to inspect source design using KLayout, SKY130 layer definitions, and finally full original GDS design. You can hide metals and DECAP cells in KLayout to make it easier to look around and compare to photos.

You can also watch video interview with decapsulation process here.

Die size 5256x3662 µm.

TT04 with metal removed, side illumination for looks:


On top metal everything is covered by power distribution and fill, so not much details below are visible:


On the right side there are few silicon doodles:








To see under top metal we need to chemically etch glass & metal layers using hydrofluoric acid (HF). Here we can see Caravel management block with RISC-V CPU at the bottom, system controller in the middle and multiple user designs covering lower half of the chip:


At higher magnification we see that all metals and polysilicon are gone, we likely only see STI (Shallow trench isolation) structures. This is IO cell:


DFF SRAM of the Caravel's RISC-V CPU. DFF memory is used to reduce tapeout risks, but much less area-efficient vs conventional SRAM array:


This is central TinyTapeout controller:


And finally, this is my design:


Chip covered by immersion oil during photography:

]]> Thu, 11 Jul 24 19:26:52 +0300