ZeptoBars - RSS feed http://zeptobars.com/en/ Microelectronics. Die-shots. Artificial intelligence. Lasers. en-us Tue, 10 Jun 2006 04:00:00 GMT Sat, 18 Aug 18 06:10:23 +0300 webmaster@zeptobars.com 120 10 <![CDATA[Phillips NE564N - PLL : weekend die-shot]]> http://zeptobars.com/en/read/Phillips-NE564N-PLL CD4046 it can operate at whopping 50MHz.
Die size 2332x1519 µm.


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Mon, 13 Aug 18 02:47:48 +0300
<![CDATA[Fairchild BSP52 - NPN Darlington BJT : weekend die-shot]]> http://zeptobars.com/en/read/Fairchild-BSP52-NPN-Darlington-BJT

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Sun, 29 Jul 18 21:36:34 +0300
<![CDATA[Ti CD4046BE - CMOS PLL / Oscillator : weekend die-shot]]> http://zeptobars.com/en/read/Ti-CD4046BE-CMOS-PLL-Oscillator-VCO-zener Ti CD4046BE is probably the most complex of these - It's a PLL with internal VCO and even zener voltage reference for external voltage regulator. It could still be useful today, if you're fine with it's 1.4Mhz frequency limit.

Die size 2271x2007 µm.



Metal etch photos are added for these who might want to recover schematics.

In the middle of the etch:


All metal etched:

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Sat, 21 Jul 18 15:55:24 +0300
<![CDATA[Diodes/Zetex BCW66H - 0.8A NPN BJT : weekend die-shot]]> http://zeptobars.com/en/read/Diodes-zetex-BCW66H-NPN-BJT


Another die showing similar pattern below pad. Die crack is mine:

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Fri, 20 Jul 18 02:39:32 +0300
<![CDATA[BB OPA134PA - FET input opamp : weekend die-shot]]> http://zeptobars.com/en/read/BB-Ti-OPA134PA-FET-opamp-trimmed-low-distortion BB OPA134PA is a trimmed, low-noise low-distortion (0.00008%) opamp with FET input stage.
Die size 1592x1077 µm.


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Sun, 15 Jul 18 14:25:24 +0300
<![CDATA[Microchip MCP6024 - CMOS R2R 10MHz opamp : weekend die-shot]]> http://zeptobars.com/en/read/Microchip-MCP6024-CMOS-R2R-opamp-trimmed Microchip MCP6024 is a CMOS R2R 10 MHz opamp with input offset trimmed down to 0.5mV.
2 identical dies inside plastic package.


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Sun, 01 Jul 18 04:58:34 +0300
<![CDATA[Nexperia BCV49 - NPN Darlington BJT : weekend die-shot]]> http://zeptobars.com/en/read/Nexperia-NXP-BCV49-BJT-NPN-Darlington

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Sat, 30 Jun 18 17:09:33 +0300
<![CDATA[ Ti SE555P - 1996 version in glass-filled DIP package: weekend die-shot]]> http://zeptobars.com/en/read/Ti-555-SE555P Ti's 555 from 2006. This is an older one, from 1996. Die here is slightly larger, transistors are square vs round and no pads in the middle of the chip.

Die size 1000x1020 µm.



Another interesting feature of many precision analog parts (including this one) - is glass-filled plastic package, which is a little painful to etch. It is more stable and have lower CTE than plain plastic - robust and economical alternative to metal-ceramic package. Glass particles here are mainly in the range from 7 to 35µm.

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Fri, 01 Jun 18 01:02:17 +0300
<![CDATA[Analog Devices AD9361 - when microchips are more profitable than drugs]]> http://zeptobars.com/en/read/AD9361-SDR-Analog-Devices-DAC-ADC-65nm still often an FPGA), external filters and PA if your task requires it.

Finally I was able to take a look inside and peek at manufacturing cost of a microelectronic device with such an exceptional added value.

After decapsulation we see 4336x4730 µm 65nm die. On top metal you can notice PLL's inductors and datecode - chip was somewhat ready 2 years before introduction:


After metallization etch we can see that most of the die area is used by RF/analog blocks:


On the right-bottom corner - main digital block, which should be the implementation of 128-tap FIR filter. In maximum magnification we can see rows on standard cells. They are placed as usual - back-2-back [PFET NFET] [NFET PFET] and hence reuse vertical lines of VCC и GND (surely power is fed from top metal all across it). You can tell PFET transistors as they are wider. Standard cell width is 1,83µm, which is consistent with 65nm manufacturing. On full resolution scale is 24.5nm per pixel.


There are small test blocks scattered across the area of the chip. Apparently they could be used only in the middle of manufacturing - there is no access to the pads from the top metal and no digital JTAG-like circuitry to access it remotely:


Capacitor arrays are the most crytical part for DAC/ADC implementation. To ensure their perfect matching dummy features are added at the sides to avoid lithography-related effects.


No SRAM arrays were found. The only regular digital structure is on the left side of this frame - but it does not look like SRAM topologies I've seen in the past. Apparently without SEM it's hard to guess what is that.


Analog is mostly FET-based:


Some more digital parts:




Finally - partially etched PLL inductance base. PLL phase noise sets the limit to digital radio performance so this is one of the most critical parts:


Let's do some rough math

Die size is ~ 21,12mm², 300mm wafer (65nm is only on 300mm ones) has approximately 65'000 mm² of usable area. So given conservative 50% yield we are getting 1538 good dies per wafer. Given wafer cost of 1600$ - manufacturing cost of each good die is ~1.04$.

NRE - 2 mask sets (400K$ each) and some tooling - will take 1mil$ total. If we conservatively estimate total manufacturing volume of 1000 wafers - NRE would add 0.64$ per good die.

Update: Many have suggested that chip of such immense complexity likely required more than 2 mask iterations even for AD. On the other hand not all test masks are full mask sets - it could have been MPW or only part of the layers changed. Also, packaging/testing cost is not included here which could be comparable to die manufacturing. Total cost of manufacturing of good packaged die should still be <5$.

Retail price of AD9361 at distributes is 275$, volume price from manufacturer is 175$.

That is quite an impressive added value! For 1,68$ of manufacturing cost we are getting 173,32$ of added value! Even Intel with their x86 or drug cartels could NOT do business like that.

But ofcourse we have to factor in R&D expenses which are very significant. From Analog Devices report for 2017 FY we can see that for 5,1bil$ of revenue they had 968mil$ of R&D expenses and gross profit of 3.061 bil$. We can split revenue form this chip in these proportions, so it will looks like this:



So one can see here that manufacturing in microelectronics is sometimes not where most of the money are spent or earned. And you don't always need 7nm to beat competition and have significant profit. But R&D & IP will be expensive and selling is as hard/expensive as developing.

You can see more microchip photos at zeptobars.com (RSS). You can also support us at Patreon to keep us going.

PS. Thanks for the chip to reader from Switzerland who wish to remain anonymous. ]]>
Fri, 25 May 18 07:18:25 +0300
<![CDATA[HP DeskJet 840c thermal inkjet printing head : weekend die-shot]]> http://zeptobars.com/en/read/HP-DeskJet-840c-thermal-inkjet-printing-head
Die size 15.12x4.39 mm.



Inkjet nozzles on a Kapton tape are likely ion-etched, laser drilled holes should have been much less perfect. On the other hand positions of nozzles are slightly not regular.


Nozzle diameter is 25µm, nozzle pitch is 75µm.

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Wed, 28 Feb 18 07:54:04 +0300