August 25, 2014
August 18, 2014
Apparently there are 30 initials of the people, involved in the design of this chip mentioned at the lower right corner. Although this chip was designed after Ti acquisition of Chipcon (that happened in January 2006), it is still marked as Chipcon.
August 4, 2014
Die size 416x362 µm, which is the smallest among microchips we've seen.
Comparing to 1-gate NAND2 Ti SN74AHC1G00 - die area here is 1/3 smaller because area below pads is not wasted and used for IO transistors and wiring. It is unclear though how they achieved decent yields (as things there might get damaged during wire bonding) - we can only tell that insulation before last metal is much thicker than usual.
Drop us a message if you have experience or knowledge on getting high-yield logic under pads - this is something we would be interested to have in our own product.
July 29, 2014
Die size 589x600 µm.
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July 27, 2014
Comparing to LM2940L or LM1117 there are more bonding pads per signal and obviously larger output transistors. Chip was soldered on copper heat spreader to help dissipate 10W+.
Die size 3075x3026 µm.
July 25, 2014
July 11, 2014