October 5, 2013

Fairchild 74F109PC - dual JK flip-flop : weekend die-shot

Fairchild 74F109PC - dual JK flip-flop, part of fastest bipolar 7400 TTL family - F.

Die size 1436x1255 µm.


September 16, 2013

Playstation 1 - MIPS R3051 CPU : weekend die-shot

Playstation 1 CPU - CXD8530CQ based on 33.8688 MHz MIPS R3051 core manufactured at 800nm technology, 3 layers of metalization.

CPU designed by LSI Logic Corp. Die size 8.15x8.1 mm.



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September 15, 2013

NXP 74HC595 : weekend die-shot

NXP 74HC595 - yet another standard logic shift register. You may compare it to Fairchild 74VHC595 and OnSemi 74HC595.

Die size 953x866 µm, 2µm manufacturing technology.



Polysilicon level:

September 14, 2013

Fairchild 74VHC595 : weekend die-shot

Fairchild 74VHC595 - standard logic chip, 8-bit shift register. You can compare it to OnSemi 74HC595.

Die size 800x690 µm. 800nm manufacturing technology.



Polysilicon level:

September 13, 2013

TNY264 : weekend die-shot

Power Integrations TNY264 - is a highly integrated ACDC converter with built-in 700V MOSFET.
Die size 2457x1306 µm.


August 26, 2013

Zilog Z80 Z0840004PSC : weekend die-shot

After taking photos of Z80-compatible CPU's from DDR and USSR we finally got the original Zilog's Z80. This chip had datecode 9012.

If you compare the dies of original Z80 and DDR/USSR ones - you can see that original Z80 has much denser peripherals layout. Also, in the middle of the die there is a word "DC", while on compatible processors there is just a blank space at the same place.

Die size 3545x3350 µm. It's area is 1.6 times smaller than T34VM1.


August 25, 2013

Altera Cyclone EP1C3 : weekend die-shot

Altera Cyclone EP1C3 is the smallest 1-st generation FPGA from Altera. It has 2910 LE, 1 PLL and 58.5 kibibit of memory (13 M4K blocks, 128x36 bit each).



On the polysilicon level we can see that each M4K block is subdivided into 2 halves (26 "rectangles" total in 2 columns). Array of logical elements is non-symmetrical, on the right side of the array right in the middle there is an PLL.

Half of die area is occupied by peripherals, which is not surprising given all the variety of supported IO standards.