May 25, 2018

Analog Devices AD9361 - when microchips are more profitable than drugs

When Analog Devices released their SDR transciever AD9361 in 2013 - it was a revolution in digital radio. SDR's were there before, but only now you can have it all: 2 channels for TX and RX with onboard 12-bit DAC/ADCs with 56MHz of RF simultanious bandwidth, local oscillators, mixers and LNA - all working in the range from 70 (TX from 47) to 6000Mhz. Using AD9361 out of the box one could implement almost any useful digital radio, with the rare exceptions of UWB and 60GHz. You only need to add data source/sink (which is still often an FPGA), external filters and PA if your task requires it.

Finally I was able to take a look inside and peek at manufacturing cost of a microelectronic device with such an exceptional added value.

After decapsulation we see 4336x4730 µm 65nm die. On top metal you can notice PLL's inductors and datecode - chip was somewhat ready 2 years before introduction:

After metallization etch we can see that most of the die area is used by RF/analog blocks:

On the right-bottom corner - main digital block, which should be the implementation of 128-tap FIR filter. In maximum magnification we can see rows on standard cells. They are placed as usual - back-2-back [PFET NFET] [NFET PFET] and hence reuse vertical lines of VCC и GND (surely power is fed from top metal all across it). You can tell PFET transistors as they are wider. Standard cell width is 1,83µm, which is consistent with 65nm manufacturing. On full resolution scale is 24.5nm per pixel.

There are small test blocks scattered across the area of the chip. Apparently they could be used only in the middle of manufacturing - there is no access to the pads from the top metal and no digital JTAG-like circuitry to access it remotely:

Capacitor arrays are the most crytical part for DAC/ADC implementation. To ensure their perfect matching dummy features are added at the sides to avoid lithography-related effects.

No SRAM arrays were found. The only regular digital structure is on the left side of this frame - but it does not look like SRAM topologies I've seen in the past. Apparently without SEM it's hard to guess what is that.

Analog is mostly FET-based:

Some more digital parts:

Finally - partially etched PLL inductance base. PLL phase noise sets the limit to digital radio performance so this is one of the most critical parts:

Let's do some rough math

Die size is ~ 21,12mm², 300mm wafer (65nm is only on 300mm ones) has approximately 65'000 mm² of usable area. So given conservative 50% yield we are getting 1538 good dies per wafer. Given wafer cost of 1600$ - manufacturing cost of each good die is ~1.04$.

NRE - 2 mask sets (400K$ each) and some tooling - will take 1mil$ total. If we conservatively estimate total manufacturing volume of 1000 wafers - NRE would add 0.64$ per good die.

Update: Many have suggested that chip of such immense complexity likely required more than 2 mask iterations even for AD. On the other hand not all test masks are full mask sets - it could have been MPW or only part of the layers changed. Also, packaging/testing cost is not included here which could be comparable to die manufacturing. Total cost of manufacturing of good packaged die should still be <5$.

Retail price of AD9361 at distributes is 275$, volume price from manufacturer is 175$.

That is quite an impressive added value! For 1,68$ of manufacturing cost we are getting 173,32$ of added value! Even Intel with their x86 or drug cartels could NOT do business like that.

But ofcourse we have to factor in R&D expenses which are very significant. From Analog Devices report for 2017 FY we can see that for 5,1bil$ of revenue they had 968mil$ of R&D expenses and gross profit of 3.061 bil$. We can split revenue form this chip in these proportions, so it will looks like this:

So one can see here that manufacturing in microelectronics is sometimes not where most of the money are spent or earned. And you don't always need 7nm to beat competition and have significant profit. But R&D & IP will be expensive and selling is as hard/expensive as developing.

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PS. Thanks for the chip to reader from Switzerland who wish to remain anonymous.